A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops

Abstract We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 μm and 281 μW. Introduction A GRO that uses a ring oscillator comprising gated inverters has been studied for use as a TDC [1]. It is noteworthy that this GROTDC has a first-order noise-shaping nature, but only its function as a first-order modulator is described in the literature. Higher-order noise shaping GROTDCs have been reported as presenting the possibility of realizing higher performance [2]. Mandai used GROs and a time difference amplifier as a time residue transmitter [3]. Instead of the GRO, Cao adopted a relaxation oscillator [4]. Gating in the GRO or the relaxation oscillator, however, causes switching noise and transistor leakage at internal nodes storing phase states. The gating transistor must be small to avoid the switching noise, which limits the oscillating frequency and performance. Moreover, the stored phase states are degraded or even lost by the transistor leakage. They are therefore unsuitable for recent leaky processes [5]. Proposed Frequency Shift Oscillator TDC (FSOTDC) Our proposed FSOTDC architecture is depicted in Fig. 1. No area-consuming capacitor or analog component is used. For that reason, it has process scalability. The FSO on the first stage outputs a frequency of FS (≈ 300 MHz: low frequency) or FF (≈ 600 MHz: high frequency). The FSO layouts of the first and second stages are identical, but their output frequencies differ slightly (FS≠FS’, FF≠FF’), which is compensated by a first-order LMS filter. The FSO presents advantages over a GRO by alleviating problems related to switching noise and transistor leakage. Furthermore, the power supply noise in the FSO is less than that in the GRO because the FSO does not cease oscillating; the fluctuation in switching current is smaller (current fluctuation: FSO=IF−IS, GRO=IF). Figure 2 depicts a timing diagram of the proposed FSOTDC. Therein, T is a sampling period, TIN1 (TIN2) signifies an input pulse width into the first-stage (second-stage) FSO, FSOOUT1 (FSOOUT2) stands for its output, D1 (D2) denotes the number of FSOOUT1 (FSOOUT2) oscillations in a sampling period, D1F denotes the number of oscillations while TIN1 is off, and QN1 (QN2) represents a quantization noise of FSOOUT1 (FSOOUT2). Herein, we define ξ as a time residue in TIN1. TIN1 and T−TIN1 are given respectively as (1) and (2) (see next page for the equations). Next, D1 and D1F, which are digital values corresponding to TIN1 and T−TIN1, are given respectively as (3) and (4) (where F F T is a constant offset). In the equations, respective QN1[n−1] and QN1[n] are quantization noises in the previous and present sampling periods. The QNP detects the third rising-edge of FSOOUT1 (see Fig. 3; because it has three flipflops) when TIN1 is off, and then it outputs TIN2. In this case, TIN2 is represented as (5). By putting (4) in (5), we can obtain (6), from which D2 is given as (7) (C1 and C2 are constants). As depicted in Fig. 3(a), the proposed QNP has three dynamic D-flipflops (DDFFs) to avoid metastability. In the FSOTDC architecture, ΔT in Fig. 3(c) might be very small because of continuous oscillation, which might cause metastability in the QNP. The DDFF depicted in Fig. 3(b) is simple and is five times faster than the conventional master–slave flipflop. By connecting the three DDFFs, the metastable period, which worsens stability and linearity, can be minimized to 0.8 ps (Fig. 3(c)). Measurement Results and Summary A test chip was fabricated using a 65 nm CMOS process (Fig. 4). The TDC core occupies 700 μm as an active area. The power supply voltage is 1.2 V. Figures 5(a) and 5(b) show the measured output spectrum of the proposed TDC with and without the LMS filter. Figure 5(c) presents a conceptual diagram of the first-order LMS filter, which estimates the ratio of the oscillation frequencies (weight: w0) between the two FSOs adaptively in the manner described above. It is apparent that second-order noise shaping is achieved by the LMS filter (see Fig. 5(b)). In the spectra, the input signal frequency is 61 kHz, the input width is 31.25 ns (the sampling rate is 16 MHz). The SNDR is 61 dB. The FSOs and QNP consume 211 μW. The peripheral buffers and flipflops consume 70 μW. The test chip performance is summarized in Table 1. Our TDC is smaller than any other TDCs (see Fig. 6). Acknowledgment This study was supported by STARC and VDEC. References [1] M. Z. Straayer et al., “A Multi-path Gated Ring Oscillator TDC with First-Order Noise Shaping,” JSSC, pp. 1089-1098, 2009. [2] T. Konishi et al., “A 40-nm 640-μm2 45-dB opampless all-digital second-order MASH ΔΣ ADC,” ISCAS, pp. 518-521, 2011. [3] S. Mandai et al., “A 128-Channel, 9ps Column-Parallel Two-Stage TDC Based on Time Difference Amplification for Time-Resolved Imaging,” ESSCIRC, pp. 119-122, 2011. [4] Y. Cao et al., “A 1.7mW 11b 1–1–1 MASH ΔΣ time-to-digital converter,” ISSCC, pp. 480-482, 2011. [5] S. Henzler, “Time-to-Digital Converters,” Springer, 2010. [6] Y-H. Seo et al., “A 0.63ps Resolution, 11b Pipeline TDC in 0.13μm CMOS,” VLSI Symp., pp. 152-153, 2011.